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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com may 2006 rev. 0 advanced* wv3eg265m72efsu-d4 white electronic designs 1gb C 2x64mx72 ddr sdram, unbuffered, pll, fbga features unbuffered 200-pin (so-dimm), small-outline, dual- in-line module fast data transfer rate: pc-2100, and pc-2700 clock speeds of 133mhz, and 166mhz supports ecc error detection and correction v cc = v ccq = +2.5v 0.2v(133 and 166mhz) bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency: ddr 266 (2, 2.5 clock), ddr333 (2.5 clock) programmable burst length (2, 4, 8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input auto and self refresh, 7.8s refresh interval (8k/64ms refresh) serial presence detect (spd) with eeprom dual rank leaded & lead-free/rohs compliant gold edge contacts jedec standard 200 pin, small-outline, so-dimm package ? pcb height option: 31.75 mm (1.25) note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option description the wv3eg265m72efsu is a 2x64mx72 double data rate sdram memory module based on 512mb ddr sdram components. the module consists of eighteen 64mx8 ddr sdrams in fbga packages mounted on a 200 pin fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change or cancellation without notice. operating frequencies ddr333@cl=2.5 ddr266@cl=2 ddr266@cl=2.5 clock speed 166mhz 133mhz 133mhz cl-t rcd -t rp 2.5-3-3 2-2-2 2.5-3-3
wv3eg265m72efsu-d4 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 0 advanced pin names symbol description a0-a12 address input ba0, ba1 bank address dq0-dq63 data input/output cb0-cb7 check bits dqs0-dqs8 data strobe ck0, ck0# clock input cke0-cke1 clock enable input cs0#-cs1# chip select input ras# row address strobe cas# column address input we# write enable dm0-dm8 data write mask v cc power supply v ss ground v ref sstl_2 reference voltage v ccspd serial eeprom positive power supply sda input/output: serial presence- detect data scl serial clock sa0-sa2 presence detect address input nc no connect pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1v ref 51 v ss 101 a9 151 dq42 2v ref 52 v ss 102 a8 152 dq46 3v ss 53 dq19 103 v ss 153 dq43 4v ss 54 dq23 104 v ss 154 dq47 5 dq0 55 dq24 105 a7 155 v cc 6 dq4 56 dq28 106 a6 156 v cc 7dq157v cc 107 a5 157 v cc 8dq558v cc 108 a4 158 nc 9v cc 59 dq25 109 a3 159 v ss 10 v cc 60 dq29 110 a2 160 nc 11 dqs0 61 dqs3 111 a1 161 v ss 12 dm0 62 dm3 112 a0 162 v ss 13 dq2 63 v ss 113 v cc 163 dq48 14 dq6 64 v ss 114 v cc 164 dq52 15 v ss 65 dq26 115 a10 165 dq49 16 v ss 66 dq30 116 ba1 166 dq53 17 dq3 67 dq27 117 ba0 167 v cc 18 dq7 68 dq31 118 ras# 168 v cc 19 dq8 69 v cc 119 we# 169 dqs6 20 dq12 70 v cc 120 cas# 170 dm6 21 v cc 71 cb0 121 cs0# 171 dq50 22 v cc 72 cb4 122 cs1# 172 dq54 23 dq9 73 cb1 123 nc 173 v ss 24 dq13 74 cb5 124 nc 174 v ss 25 dqs1 75 v ss 125 v ss 175 dq51 26 dm1 76 v ss 126 v ss 176 dq55 27 v ss 77 dqs8 127 dq32 177 dq56 28 v ss 78 dm8 128 dq36 178 dq60 29 dq10 79 cb2 129 dq33 179 v cc 30 dq14 80 cb6 130 dq37 180 v cc 31 dq11 81 v cc 131 v cc 181 dq57 32 dq15 82 v cc 132 v cc 182 dq61 33 v cc 83 cb3 133 dqs4 183 dqs7 34 v cc 84 cb7 134 dm4 184 dm7 35 ck0 85 nc 135 dq34 185 v ss 36 v cc 86 nc 136 dq38 186 v ss 37 ck0# 87 v ss 137 v ss 187 dq58 38 v ss 88 v ss 138 v ss 188 dq62 39 v ss 89 nc 139 dq35 189 dq59 40 v ss 90 v ss 140 dq39 190 dq63 41 dq16 91 nc 141 dq40 191 v cc 42 dq20 92 v cc 142 dq44 192 v cc 43 dq17 93 v cc 143 v cc 193 sda 44 dq21 94 v cc 144 v cc 194 sa0 45 v cc 95 cke1 145 dq41 195 scl 46 v cc 96 cke0 146 dq45 196 sa1 47 dqs2 97 nc 147 dqs5 197 v ccspd 48 dm2 98 nc 148 dm5 198 sa2 49 dq18 99 a12 149 v ss 199 nc 50 dq22 100 a11 150 v ss 200 nc
wv3eg265m72efsu-d4 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 0 advanced functional block diagram a0 sa0 serial pd sda a1 sa1 a2 sa2 ba0, ba1 a0-a12 ras# ba0, ba1: ddr sdrams a0-a12: ddr sdrams ras#: ddr sdrams cas#: ddr sdrams cke0: ddr sdrams cke1: ddr sdrams we#: ddr sdrams cas# cke0 cke1 we# v ref v ss ddr sdrams ddr sdrams dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq dq dq dq dq dq dq dq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm cs# dqs dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm0 cs0# dq dq dq dq dq dq dq dq wp scl dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq cs1# dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dm7 dqs7 dm1 dqs1 dm6 dqs6 dq dq dq dq dq dq dq dq dm cs# dqs dm2 dqs2 dm5 dqs5 dm cs# dqs dm cs# dqs dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dq dm3 dqs3 dm4 dqs4 dq dq dq dq dq dq dq dq dm cs# dqs dq dq dq dq dq dq dq dq dm cs# dqs v ccspd v cc ddr sdrams spd/eeprom cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dq dq dq dq dq dq dq dq dm8 dqs8 dm cs# dqs dq dq dq dq dq dq dq dq dm cs# dqs pll ck0 ck0# 120 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 note: all resistor values are 22 ? 5% unless otherwise speci? ed.
wv3eg265m72efsu-d4 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 0 advanced dc electrical characteristics parameter/condition symbol min max units notes supply voltage drr266/ddr333 (nominal v cc 2.5v) v cc 2.3 2.7 v i/o supply voltage drr266/ddr333 (nominal v cc 2.5v v ccq 2.3 2.7 v i/o reference voltage v ref 0.49 v cc 0.51 v cc v1 i/o termination voltage v tt v ref - 0.04 v ref + 0.04 v 2 input logic high voltage v ih(dc) v ref + 0.15 v cc + 0.30 v input logic low voltage v il(dc) -0.3 v ref - 0.15 v input voltage level, ck and ck# v in(dc) -0.3 v ref + 0.30 v input differential voltage, ck and ck# v id(dc) 0.3 v ref + 0.60 v 3 input crossing point voltage, ck and ck# v ix(dc) 0.3 v ref - 0.60 v input leakage current addr cas#, ras#, we# i i -36 36 a cs#, cke -18 18 a ck, ck# -10 10 a dm -4 4 a output leakage current i oz -10 10 a output high current (normal strength) v out = v +0.84v i oh -16.8 ma output high current (normal strength) v out = v tt - 0.84v i ol 16.8 ma output high current (half strength) v out = v tt - 0.45v i oh -9 ma output high current (half strength) v out = v tt - 0.45v i ol 9ma notes: 1 v ref is expected to equal to 0.5*v ccq of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed +/-2 percent of the dc value. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 3. v id is the magnitude of the difference between the input level on ck and the input level of ck#. absolute maximum ratings symbol parameter value units v in , v out voltage on v cc pin relative to v ss -0.5 ~ 3.6 v v cc , v ccq voltage on v cc & v ccq supply relative to v ss -1.0 ~ 3.6 v v ref voltage of v ref supply relative to v ss -1.0 ~ 3.6 v t stg storage temperature -55 ~ +150 c t a operating temperature 0 ~ 70 c p d power dissipation 18 w i os short circuit output current 50 ma notes: permanent device damage may occur if absolute maximum ratings are exceed. functional ioeration should be restricted to recommended operation conditions. exposing to higher than recommended voltage for extended periods of time could affect device reliability.
wv3eg265m72efsu-d4 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 0 advanced input/output capacitance ta=25c, f=100mhz parameter symbol min max unit input capacitance (a0~a12, ba0~ba1, ras#, cas#, we#) c in 131 49 pf input capacitance (cke0, cke1) c in 2 17.5 26.5 pf input capacitance (cs0# - cs1#) c in 3 17.5 26.5 pf input capacitance (clk0, clk0#) c in 46 7.5pf input capacitance (dm0~dm8) c in 511 13 pf input capacitance (dq0~dq63), (cb0~cb7) c out 111 13 pf ac operating conditions parameter symbol min max unit ac input high (logic 1) voltage v ih (ac) v ref + 0.31 - v ac input high (logic 0) voltage v il (ac) - v ref - 0.31 v input differential voltafe, ck and ck# inputs v id (ac) 0.7 v cc + 0.6 v input crossing point voltage, ck and ck# input vix(ac) 0.5*v cc - 0.2 0.5*v cc + 0.2 v
wv3eg265m72efsu-d4 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 0 advanced i cc specifications and conditions v cc , v ccq = +2.5v 0.2v sym parameter/condition max units ddr333 @cl=2.5 ddr266 @cl=2 ddr266 @cl=2.5 i cc0* operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 1,270 1,180 1,180 ma i cc1* operating current: one device bank; active-read-precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); iout = 0ma; address and control inputs changing once per clock cycle 1,540 1,450 1,450 ma i cc2p** precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) 370 370 370 ma i cc2f** idle standby current: cs# = high; all device banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle. vi n = v ref for dq, dqs, and dm 820 820 820 ma i cc3p** active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low 820 820 820 ma i cc3n** active standby current: cs# = high; cke = high; one device bank active; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 1,090 1,090 1,090 ma i cc4r* operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma 1,585 1,450 1,450 ma i cc4w* operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle 1,675 1,495 1,495 ma i cc5** auto refresh burst current: t refc = t rfc (min) 3,970 3,790 3,790 ma i cc6** self refresh current: cke 0.2v 370 370 370 ma i cc7* operating current: four device bank interleaving reads (burst = 4) with auto precharge, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read, or write commands 3,565 3,250 3,250 ma note: i cc speci? cation is based on samsung components. other dram manufacturers speci? cation may be different. *: value calculated as one module rank in this operating condition, and all other module ranks in i cc2p (cke low) mode. **: value calculated re? ects all module ranks in this operating condition.
wv3eg265m72efsu-d4 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 0 advanced ddr sdram component electrical characteristics and recommended ac operating conditions v cc = v ccq = +2.5v 0.2v ac characteristics 335 262 265 units parameter symbol min max min max min max row cycle time trc 60 65 65 t ck refresh row cycle time trfc 72 75 75 ps row active tras 42 70k 45 120k 45 120k ps ras# to cas# delay trcd 18 20 20 t ck row precharge time trp 18 20 20 ns row active to row active delay trrd 12 15 15 ns write recovery time twr 15 15 15 ns last data in to read command twtr 111ns clock cycle time cl = 2.5 t ck (2.5) 6 12 7.5 12 7.5 12 ns cl =2 t ck (2) 7.5 12 7.5 12 10 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs-out access time from ck/ck# t dqsck -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns output data access time from ck/ck# tac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns data stobe edge to output data edge t dqsq 0.45 0.5 0.5 ns read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck ck to vaild dqs-in t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs-in setup time twpres 000ns dqs-in hold time twpre 0.25 0.25 0.25 t ck dqs falling edge to ck rising-setup time t dss 0.2 0.2 0.2 t ck dqs falling edge to ck rising-hold time tdhs 0.2 0.2 0.2 t ck dqs-in high level width tdqhs 0.35 0.35 0.35 t ck dqs-in low level width tdqsl 0.35 0.35 0.35 t ck address and control input setup time (fast) tisf 0.75 0.9 0.9 ns address and control input hold time (fast) tihf 0.75 0.9 0.9 ns address and control input setup time (slow) tiss 0.8 1.0 1.0 ns address and control input hold time (slow) tihs 0.8 1.0 1.0 ns data-out high impedance time from ck/ck# thz -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns data-out low impedance time to ck/ck# tlz -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns mode register set cycle tmrd 12 15 15 ns dq & dm setup time to dqs tds 0.45 0.5 0.5 ns dq & dm hold time to dqs tdh 0.45 0.5 0.5 ns control & address input pulse width tipw 2.2 2.2 2.2 ns dq & dm input pulse width tdipw 1.75 1.75 1.75 ns exit self refresh to non-read command txsnr 75 75 75 ns * ac speci? cation is based on samsung components. other dram manufactures speci? cation may be different. continued on next page
wv3eg265m72efsu-d4 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 0 advanced ddr sdram component electrical characteristics and recommended ac operating conditions (continued) v cc = v ccq = +2.5v 0.2v ac characteristics 335 262 265 units parameter symbol min max min max min max exit self regresh to read command t xsrd 200 200 200 t ck refresh interval time t refi 7.8 7.8 7.8 s output dqs vaild window t qh t hp -t qhs t hp -t qhs t hp -t qhs ns clock half period t hp t clmin or t chmin t clmin or t chmin t clmin or t chmin ns data hold skew factor t qhs 0.55 0.75 0.75 ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 ns active read with auto precharge command t rap 18 20 20 ns auto precharge write recovery + precharge time t ral t wr /t ck + t rp /t ck t wr /t ck + t rp /t ck t wr /t ck + t rp /t ck t ck * ac speci? cation is based on samsung components. other dram manufactures speci? cation may be different.
wv3eg265m72efsu-d4 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 0 advanced * all dimensions are in millimeters and (inches) 200-pin ddr so-dimm dimensions ordering information for d4 part number speed cas latency t rcd t rp height* wv3eg265m72efsu335d4xxx 166mhz/333mbps 2.5 3 3 31.75 (1.25") max wv3eg265m72efsu262d4xxx 133mhz/266mbps 2 2 2 31.75 (1.25") max wv3eg265m72efsu265d4xxx 133mhz/266mbps 2.5 3 3 31.75 (1.25") max notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult f actory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option 3.80 (0.150 ) max 1.10 (0.043) 0.90 (0.035) pin 1 67.75 (2.667) 67.45 (2.656) 20.00 (0.787) typ 1.80 (0.071) (2x) 0.60 (0.024) typ 0.45 (0.018) typ 4.10 (0.161) 2x 3.90 (0.154) pin 199 pin 200 pin 2 front view 2.15 (0.085 6.00 (0.236) 63.60 (2.504) 47.40 (1.866) typ 4.2 (0.165) typ 11.40 (0.449) typ 2.55 (1.00) 1.00 (0.039) typ 31.90 (1.256) 31.60 (1.244) typ back view
wv3eg265m72efsu-d4 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 0 advanced part numbering guide wv 3 e g 2 65m 72 e f s u xxx d4 x x x wedc memory (sdram) ddr gold dual rank depth (x64 5indicates with pll) bus width component width x8 fbga 2.5v unbuffered speed (mb/s) package 200 pin industrial temp option (for commercial leave "blank" for industrial add "i") component vendor name (m = micron) (s = samsung) (n = nanya) g = rohs compliant (add g for rohs,leave blank for leaded)
wv3eg265m72efsu-d4 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 0 advanced document title 1gb C 2x64mx72 ddr sdram, unbuffered, with pll, fbga dram die options: ? samsung: c-die ? micron: t27z: d-die, will move to t37z:f q206 ? nanya: b-die revision history rev # history release date status rev 0 created may 2006 advanced

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